a) Field of the Invention
The present invention relates to a wiring forming method used in semiconductor integrated circuit or the like.
b) Description of the Related Art
In a process of manufacturing a semiconductor integrated circuit, wirings for connecting respective elements are formed after the respective elements are formed. Process of forming wirings, generally, is achieved by such procedure as follows. First, contact holes are formed to expose electrode portions of respective elements (such as diffusion layers, polycrystalline silicon regions or the like) through an insulating layer which covers the whole surface of the substrate. Then, after depositing a metal layer as of aluminum (Al) over the whole surface of the insulating layer, selective etching of the metal layer using a mask of photo-resist is carried out to form wirings connecting the electrodes of the respective elements. Further, an inter-layer insulating film is formed, and an upper level wiring for connecting the wirings is formed by a similar procedure. Here, to obtain a normally operable semiconductor integrated circuit, it is necessary to obtain a perfect electrical contact between the substrate or a lower level wiring which has exposed portion to be contacted via contact hole and the wiring. Following methods are employed heretofore to satisfy this requirement.